1. Technical Field
The present invention relates to network interfacing and more particularly, to methods and systems for buffering data between a host bus interface and a media access controller accessing Ethernet media.
2. Background Art
Network interface devices handle packets of data for transmission between a host computer and a network communications system, such as a local area network. The host computer may be implemented as a client station, a server, or a switched hub. One primary function of the network interface device is to buffer data to compensate for timing discrepancies between the clock domain of the host computer and the clock domain of the network.
Network interface devices typically include a first in, first out (FIFO) buffer memory for storing transmit and receive data, where the transmit data is stored in a transmit FIFO buffer prior to transmission on the network media by a media access controller (MAC), and receive data is stored in a receive FIFO by the MAC prior to transfer to the host computer via the host computer bus interface.
One disadvantage with the use of a FIFO queue for a transmit buffer or a receive buffer is the increased latency encountered during the buffering process. The latency of the network interface device is the time delay between the time that a data frame is supplied to the network interface device and the time the data is transmitted on the network media, or vice versa.
An additional problem concerns flow control of the buffer; i.e., controlling the flow of data into and out of the buffer. This problem is complicated by the use of different clock domains by the host computer and the network interface device. For example, buffer overflow or underflow can occur when the time domains between the host bus and the network media are unsynchronized. Overflow occurs when the rate of data stored into the buffer is faster than the data can be removed. An overflow condition may result in lost data and/or wasteful retransmissions. Conversely, underflow occurs if data is removed from the FIFO buffer faster than the data can be supplied, which may result in the incomplete transmission of a transmit packet by the MAC.
Hence, the non-synchronous relationship between the host bus clock domain and the network clock domain have required the use of FIFO buffers to compensate for timing discrepancies between the host computer and the network.
There is a need for an arrangement that enables use of a random access memory in a network controller, as opposed to a FIFO buffer, to compensate for timing discrepancies between the host computer and the network.
There is also a need for an arrangement enabling the use of a random access memory as a buffer in a network interface device, where potential synchronization problems between the clock domain of the host computer and the clock domain of the network are resolved to enable efficient control of the random access memory during the writing and reading of transmit or receive data.
There is also a need for an arrangement in a network interface device that enables a read controller to read data from a buffer memory onto a host bus with minimal latency and minimal complexity in the network interface device design.
These and other needs are attained by the present invention, where read and write counters having read and write pointer values and are each configured to change a single bit each time the corresponding pointer value is incremented, and a synchronization circuit selectively sets a full or empty flag based on a comparison of the read and write pointer values.
According to one aspect of the present invention, a method in a network interface device comprises writing data into a random access memory in the network interface device based on a first clock, changing a single bit of a write pointer value in response to each occurrence of the writing step, reading stored data from the random access memory based on a second clock independent from the first clock, changing a single bit of a read pointer value in response to each occurrence of the reading step, comparing the read pointer value and the write pointer value, and selectively setting one of a full and empty flag based on the comparing step. The changing of a single bit in the read and write pointer values ensures that no errors occur due to transitional states during changing of values. Hence, accuracy of full and empty flag values is ensured by eliminating the synchronization problems that normally occur in a multi-clock environment.
Another aspect of the present invention provides a network interface device for storing a data frame, comprising a random access memory, a write controller configured for writing data to the random access memory according to a first clock, the write controller including a write counter configured for changing a single bit of a write pointer value in response to writing the data into a corresponding memory location in the random access memory, a read controller configured for reading stored data from the random access memory according to a second clock independent from the first clock, the read controller including a read counter configured for changing a single bit of a read pointer value in response to reading the stored data from a corresponding memory location in the random access memory, and a comparison circuit for selectively determining one of a full condition and an empty condition in the random access memory based on the write pointer value and the read pointer value, independent of the first and second clocks. The changing of a single bit by the counters enables the comparison circuit to accurately determine of the full or empty state of the random access memory independent of the different clocks used in the system.
Still another aspect of the present invention provides a network interface device for storing a data frame, comprising a random access memory, a write controller configured for writing the frame into the random access memory according to a first clock, a read controller configured for reading the frame from the random access memory according to a second clock independent from the first clock, a write counter configured for changing a single bit of a write pointer value in response to a received write signal from the write controller, a read counter configured for changing a single bit of a read pointer value in response to a received read signal from the read controller, and a synchronization circuit configured for selectively generating a signal indicating one of a full or empty condition of the random access memory based on the write pointer value and the read pointer value.
Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.